ASML, TSMC, Samsung and Intel said on 8 September they are working together to move chipmaking photomasks from the current six inch standard to twelve inches, targeting a pilot line in 2031 and full readiness for advanced node production in 2033. The masks sit inside ASML’s High NA EUV lithography systems, the newest class of machine built to print the smallest features in AI chips and other leading edge silicon.
The problem already exists in fabs today. High NA EUV is entering production on the old six inch masks, and at that size, large complex chips such as AI accelerators often cannot fit on a single mask. They have to be split across multiple exposures and stitched together during manufacturing, which adds cost and can introduce defects at the seams. TSMC said a twelve inch format would raise fab productivity and remove that stitching constraint entirely.
Intel is furthest along in using the current tool, having pushed more than a million wafers through High NA EUV steps across testing and volume production, including on layers of its Panther Lake processors. Samsung has committed to High NA EUV for DRAM manufacturing by 2028, two years ahead of TSMC’s own 2030 target. Chipmakers rarely coordinate this openly on shared infrastructure, which signals how expensive it would be for any one to solve the mask problem alone.
The seven year gap between this week’s agreement and a working twelve inch line is the detail worth sitting with. AI accelerator demand the industry calls urgent today will be answered, if the plan holds, by tooling not ready until 2033. Whether stitched six inch masks stay workable that long, or whether someone finds a shorter path first, is not something Tuesday’s announcement addressed.
